1. Field of the Invention
The invention relates to the field of non-volatile MOS memory cells.
2. Prior Art
In some applications, it is necessary to retain the information stored in random-access memories (RAMs) when power is interrupted or fails. Most often the power supplies for these memories have a considerable amount of capacitance, and thus store sufficient energy to operate the memory for a second or more after the interruption of power. The interruption of power, however, is immediately sensed and measures taken to retain the information in the RAMs in some form which will not be lost when the energy in the power supplies dissipates.
Numerous prior art RAM cells are known which retain information when deactivated. One category of these devices employs a silicon nitride layer (NMOS devices) to selectively store charge when the cell is powered down. These cells are relatively large in area and require resetting after each power-down/retention cycle.
Floating gate memory devices are employed in conjunction with bistable circuits to form a non-volatile RAM cell. These memory devices are typically used as memory cells in read-only memories. The closest prior art known to Applicant was disclosed at the IEEE International Solid-State Circuit Conference, Feb. 16, 1978, Session IX: Static and Nonvolatile Memories, in a paper entitled "A 256-Bit Nonvolatile Static RAM" by Harari, et al. In this non-volatile RAM cell, floating gate memory devices are employed as the control transistors in a bistable (flip-flop) circuit. This cell has a number of disadvantages, including the fact that the charging and discharging of the floating gate must be carefully controlled if proper operation of the cell is to be obtained. Moreover, during a power-down/retention cycle, the complement of the data is obtained, not the true data.